The development of the application of integrated circuits shows that more complex functions are realized by stacking two or more chips. Several technologies for stacking the chips and for their contacting are known. A generally known embodiment for increasing the packaging density is to stack unpackaged components using an adhesive medium for stacking the chips on top of each other, with connections from each chip to the substrate or to another chip via wire bonds.
U.S. Patent Application Publication 2003/0015803 discloses a multichip module with two or more stacked bare chips. Here, the first chip is mounted directly on a substrate and a further chip is spaced apart by a spacer of smaller dimensions attached to adjacent chips by an adhesive. The spacer prevents the chips from directly contacting each other and it allows wire-bonding of each of the stacked chips to a substrate, by using the unused space beside the spacer and between the adjacent chips. To prevent damage to the bond wires, the spacer is shorter on the sides facing the bonding pads of the chips and the height of the spacer is determined by the desired wire bond connections and the used bonding tool.
The spacer must include design considerations for wire bonding, and position between the chips requires a certain account of the bond wires and a certain design and positioning. This consideration is relevant for both the upper and bottom chips, with respect to the spacer and with respect to the adhesive on both sides of the spacer. Since a correction of the position of the chip is not possible, misplacement will cause problems in wire bonding and in the reliability requirements. Moreover, the optimum dispensing of the adhesive between spacer and chip is not a simple process. Consequently, the assembly process is very time consuming, i.e., long processing time and the extension of this basic technology to a stack with more than two chips increases the complexity and increases its costs. In addition, if the chips get thinner or if a redistribution layer (RDL) is required, the assembly process and handling becomes more difficult.
Additionally, one disadvantage of the stacking of so-called bare chips, is that cracks or other mechanical damage can arise, in the course of handling, which may also have effects on the active chip side and consequently in the reliability of the stack.
U.S. Patent Application Publication No. 2005/0012196 also discloses a multichip device in a stacked configuration that uses a spacing element for allowing increased device density. The spacing element is an interposer device having a T-shape in cross-section. The base of the vertical stem of the T-interposer is attached to a substrate or the active side of a chip and its T-bar member extending across the stem, forms a horizontal surface for stacking of a further chip.
This configuration utilizes two adhesive areas, between the T-interposer and the substrate or the bottom chip, as well as between the T-interposer and the upper chip. Moreover, the configuration also uses unpacked chips with the above-explained disadvantages.
In U.S. Patent Application Publication No. 2004/0126910 the central bond pads on the side of memory chips and their wire bond connections, are covered by a protective encapsulation. The encapsulation has a flat upper surface and is higher than the loops of the covered wire bond connections. This permits stacking of the chips with vertical spacing. However, the encapsulation attached on the active side avoids one of the adhesive areas, but it is inapplicable to every chip.